CS520 S99 Midterm
Please email me your answer by 3/14 Sunday 11:59pm
a) Amdal Law. For an application where CPU execution takes 50% of the time,
what is overall speedup in term of %, if we just improve CPU?
b) What is the execution time for a code segment with 8000 sequential
instructions (no jump), running on a machine with an average CPI of 1 and
500MHz clock rate?
a) What is IEEE single precison floating point representation of 9.0 in
b) Repeat radix-4 SRT division for 63/6 with 6 bit registers, and show
steps similar to Figure A.35.
Assume a write back cache with cache size of 256Bytes, block size of 32Bytes,
double precision floating point arrays a and b, arrray a has 2 rows and
8 columns, array b has 8 rows and 2 columns. Array a is allocated with
memory starting at address 64 (decimal), array b is allocated with memory
starting at address 192.
for (i=0; i<2; i++)
for (j=0; j<8; j++)
= b[j] +5.0;
a) It is a direct-mapped cache. Calculate the cache misses for accessing
arrays a and b.
b) It is a 2-way set associative cache. Calculate the cache misses
for accessing arrays a and b.